As integrated circuit (IC) chip technology matures, smaller die packages are possible due to smaller and denser ICs. In many cases multiple small IC chips may be packaged together in a common package. In one example, the multiple IC chips may comprise components or systems that function together as part of a larger component or system (e.g., system-in-package (SiP), etc.). The IC chips may be mounted to a common carrier (e.g., substrate, wafer, panel, etc.) or base layer, for instance. The IC chips may be interconnected by one or more wiring or interconnection layers (e.g., metallization layers) associated with the common carrier. Additionally, connection terminals (such as flip-chip bumps, for example) can be added to the metallization layer(s) of the common carrier for connection of the die package to a circuit board, or the like.
In some cases, several packages containing the multiple IC chips may be coupled to a common SiP substrate, or the like, which may be coupled to the circuit board via terminals (e.g., flip-chip bumps, wire bonds, etc.) on the SiP substrate. In other cases, to manage the potential wiring congestion of such an arrangement and to fan out the connections to a workable scale, a silicon interposer may be used between the die packages and the SiP substrate.
For example, the dies may be coupled to the silicon interposer via fine pitch connections (e.g., ˜10 um diameter terminals) and the silicon interposer may be coupled to the SiP substrate via larger pitch connections (e.g., ˜100 um diameter terminals). The SiP substrate may then be coupled to the circuit board, or the like, via terminals sized to accommodate the circuit board.
The silicon interposer often has topside and backside metal layers formed using a similar process as that of the metallization layers of the silicon IC chips. Metallic through-silicon vias (TSVs) can be formed through the silicon interposer, which route connections on the topside to connections on the backside of the silicon interposer.
The use of a silicon interposer to couple multiple dice to an SiP substrate, for example, is often referred to as a 2.5D packaging scheme, and it offers increased capacity and performance as compared to packaging schemes without the silicon interposer. Further, some 3D packaging schemes include stacking two or more dice on top of each other, with the bottom-most die (or dice in multiple-stack arrangements) coupled to the silicon interposer.
However, there can be a variety of challenges to implementing these arrangements. For example, consistent die placement accuracy, along with alignment requirements between dice can be problematic. This is further complicated by the fine pitch connection terminals of the dies. Also, a desired reliability of a fine pitch redistribution layer (RDL) (e.g., a line/space width of ˜2-5 um) can be difficult to achieve over a molded surface (e.g., die package overmold). Further, it can be non-trivial to achieve a desired yield and reliability of metal traces across a silicon/overmold border.